Silicon Quality and Reliability Engineer, Google Cloud
Google · Zhubei, Taiwan | Taipei, Taiwan
In this role, you will help to build the System-on-a-chip (SoCs) that power these facilities by driving quality and reliability processes in High Volume Manufacturing (HVM) from an Integrated Circuit perspective. You will partner with cross-functional teams to develop HVM quality and reliability specifications while collaborating with global hardware teams, silicon design, validation, and engineering groups to ensure fleet excellence.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Responsibilities
- Perform end-to-end electrical and physical failure analysis on Central Processing Unit/Tensor Processing Unit (CPU/TPU) devices from prototype stages through manufacturing.
- Utilize advanced hardware and software techniques, such as Emission Microscope (EMMI) and Optical Beam Induced Resistance Change (OBIRCH), to localize defects within reasoning and memory blocks.
- Execute destructive techniques including delayering, cross-sectioning, and high-resolution imaging (e.g., Scanning Electron Microscope (SEM), Transmission Electron Microscope (TEM), Focused Ion Beam (FIB)) to visualize and identify physical defects.
- Partner with design, product, and foundry teams to interpret failure data and implement actions for design or process improvements.
- Generate Failure Analysis (FA) reports and develop novel workflows tailored for advanced technology nodes and three-dimensional (3D) packaging architectures.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 2 years of experience in semiconductor failure analysis or a related process engineering role.
- Experience with standard failure analysis lab equipment (e.g., Curve Tracer, Focused Ion Beam (FIB), Scanning Electron Microscope (SEM)).
Preferred qualifications:
- Experience with Chip-on-Wafer-on-Substrate (CoWoS) packaging, interconnect analysis or stress diagnostics.
- Experience with advanced diagnostics tools (e.g., Utilize scan diagnosis, Automatic Test Pattern Generation (ATPG)), and memory Built-In Self-Test (BIST) tools for fault isolation.
- Experience with CPU/TPU specializations, diagnosing architecture-specific symptoms including cache bit flips, scanning chain issues, and Serializer/Deserializer Input/Output (SerDes I/O) failures.
- Experience with stress diagnostics.
- Knowledge of semiconductor device physics, transistor operation (e.g., Fin Field-Effect Transistor/Gate-All-Around Field-Effect Transistor (FinFET/GAA)), and fabrication processes.