Senior Silicon Validation Engineer, Networking

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

• Define, develop and execute post-silicon validation content on both pre-silicon setups and real silicon platforms in the lab.
• Drive silicon from being a chip towards becoming a product.
• Debug and investigate issues along cross-functional teams such as Firmware (FW), Software (SW), Design, Design Verification (DV), Architecture (ARCH) and multiple production teams.
• Provide a quality functional coverage for Google designs.
• Test Development and Automation, Design, implement, and maintain validation tests using scripting and programming languages (e.g., Python, C/C++) to verify SmartNIC functionality and performance.

Minimum qualifications:

• Bachelor's degree in Electrical/Computer Engineering, Computer Science, related field, or equivalent practical experience.
• 5 years of experience with functional tests for silicon validation (i.e., writing in C or C++).
• 5 years of experience in silicon bring-up, functional validation, characterizing, and qualifying silicon.

Preferred qualifications:

• Experience with hardware prototyping, including hardware/software integration (i.e., pre-silicon use of emulation, software-based test, and diagnostics development).
• Experience and knowledge in packet processing, data path, packet buffering, scheduler, networking protocols offload engine.
• Knowledge in L1/L2 layers, Ethernet SerDes, MAC+PCS.
• Knowledge of System on a chip (SoC) architecture, including boot flows and embedded processors/firmware.
• Ability to focus on validating key features, including Ethernet interface (SerDes, MAC + PCS) PCIe high-speed interface, network protocols (e.g., Ethernet, RDMA, NVMe), packet processing, data path, packet buffering, and embedded processors/firmware.