Senior CPU Performance Architect
Google · New Taipei, Taiwan | Zhubei, Taiwan
About this role
Google is hiring a senior-level Hardware Engineer in the software engineering function based in New Taipei, Taiwan | Zhubei, Taiwan. The posting calls out experience with Python, C, Linux, Machine Learning.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- senior
- Track
- Individual contributor
- Employment
- Full-time
- Location
- New Taipei, Taiwan | Zhubei, Taiwan
- Posted
- May 6, 2026
More roles at Google
Job description
from Google careersBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be the key contributor to improve processor instruction set architecture, develop micro-architecture features, and to deliver Google’s SoC products. You will have the opportunity to collaborate with Google’s Android applications and AI teams to plan and conduct application and benchmark performance analysis.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Plan and evaluate ARM’s architecture features from both architecture and performance aspects.
- Develop a performance model for performance analysis and micro-architecture study.
- Define and write CPU subsystem architecture specifications.
- Lead collaborate with RTL, design verification, and physical design teams to develop CPU implementation.
- Drive performance correlation between the performance model and RTL implementation, including micro-benchmark development and pre-silicon and post-silicon performance bug triage.