ASIC Design Verification Engineer
Cisco · San Jose, CA · Product and Engineering
About this role
Cisco is hiring a mid-level Hardware Engineer in the software engineering function based in San Jose, CA. The posting calls out experience with Python, Networking, Testing and roughly 5+ years of relevant work. Listed education preference: a bachelor's degree or equivalent. Compensation is listed at $152,500–$219,200 per year.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- mid
- Track
- Individual contributor
- Employment
- Full-time
- Location
- San Jose, CA
- Experience
- 5+ years
- Education
- Bachelor's degree
- Department
- Product and Engineering
- Posted
- Mar 12, 2026
More roles at Cisco
Job description
from Cisco careersJob posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
Meet the Team
The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms powering Cisco’s core Switching, Routing, and Wireless products. We design networking hardware for enterprises, service providers, the public sector, and nonprofit organizations worldwide. As part of the team behind Cisco Silicon One—the industry’s only unified silicon architecture spanning top-of-rack switches to web-scale data centers—you’ll help shape Cisco’s groundbreaking solutions by designing, developing, and testing some of the most advanced ASICs in the industry.
Your Impact
As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco’s revolutionary data center solutions. You’ll architect and develop DV infrastructure, create and execute comprehensive test plans, and ensure robust verification and coverage for complex chips. Your collaboration with designers, architects, and software teams will help guarantee seamless integration and optimal performance of Cisco’s hardware platforms. You will:
- Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure
- Build DV environments from scratch for block and cluster levels
- Develop, implement, and enhance test plans and tests for block and cluster verification, using both constraint-random and directed stimulus