Principal Software Engineer
Cadence Design Systems · Noida, India
principal
Software Engineer
tech_leadership
5-10 yrs Bachelor's
· Posted Apr 20, 2026
About this role
Cadence Design Systems is hiring a principal-level Software Engineer based in Noida, India. The posting calls out experience with Python, C, Bash, Testing and roughly 5–10 years of relevant work. Listed education preference: a bachelor's degree or equivalent.
- Role
- Software Engineer
- Function
- software engineering
- Level
- principal
- Track
- Tech leadership
- Employment
- Full-time
- Location
- Noida, India
- Experience
- 5–10 years
- Education
- Bachelor's degree
- Posted
- Apr 20, 2026
AI Summary
Design and implement comprehensive verification environments for digital IPs and SoCs using UVM and SystemVerilog. Develop test plans, coverage monitors, and automated test suites while debugging failures and driving coverage closure. Requires 5-10 years of verification experience with strong expertise in SVA, UVM, Verilog/SystemVerilog, and EDA tools.
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Job description
from Cadence Design Systems careersAt Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- Design and implement a full, dedicated, and flexible (e.g., UVM based) verification environment
- Involved with all aspects of pre-silicon verification at unit and system level to ensure functional correctness and performance of the overall system-level solution.
- Defining verification strategy from IP to top digital integration
- Define requirements for block level and full-chip level verification infrastructure
- Create test plans for unit-level and chip-level verification and post-silicon validation
- Debug failures and drive in-time resolution of bugs
- Create coverage monitors and drive coverage to required quality targets
- Develop tools, test benches, and test suites (UVM, C++/C ) to execute test plans.
- Write functional coverage, analyze both code and functional coverage, and close coverage gaps
- Develop and use unit level test benches that use functional tests as well as constrained random stimulus.
- When needed, define and develop formal verification environment
Skills
- BS or MS in EE, CS or related engineering discipline
- 5-10 years of demonstrated experience in verification of IPs, Digital Design and SoCs
- Strong experience in design and verification standards and methodologies (SVA, UVM/OVM).
- In-depth knowledge of Verilog and System Verilog HDL and experience with simulators and waveform debugging tools
This is an excerpt. Read the full job description on Cadence Design Systems careers →