Digital Design Engineer
Broadcom · USA-TX-Austin - River Place B7
About this role
Broadcom is hiring a mid-level Systems Engineer in the operations function based in USA-TX-Austin - River Place B7. The posting calls out experience with Python, Frontend Development. Compensation is listed at $101,000–$162,000 per year.
- Role
- Systems Engineer
- Function
- operations
- Level
- mid
- Track
- Individual contributor
- Employment
- Full-time
- Location
- USA-TX-Austin - River Place B7
- Posted
- May 8, 2026
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Job description
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Job Description:
Looking for a digital logic design engineer to work on challenging high speed design of complex logic for Ethernet and PCIE cores used across multiple chips. You will be responsible for the front end design and verification of design blocks for these cores. Specific duties will include, but are not limited to architecture definition, logic design, synthesis, constraint development; design verification through simulation, formal verification, along with analysis of timing from the physical implementation. You will design logic blocks from systems requirements documents and will simulate and debug designs with Verilog simulation.
Job Requirements:
A Bachelor’s Degree in Electrical and Electronic Engineering or Computer Science with 5+ years relevant industry experience or a Masters degree in Electrical and Electronic Engineering or Computer Science with 3+ years relevant industry experience or a PhD degree with no experience.
Some experience with PCIE or ethernet protocols
Experience in all aspects of the process flow from high-level RTL design to synthesis, constraint development and verification
Effective RTL coding styles
Demonstrate the ability to work through technology challenges and physical implementation issues associated with high-performance design implementations.
Additionally, the candidate should possess excellent communication and inter-personal skills to work closely with other team members and demonstrate an ability to learn new tools quickly.
Must have legal authorization to work in the US.
The candidate should have expertise in some of the following areas:
Verilog HDL for design and simulation
Synopsys design compiler for synthesis
Experience using PrimeTime
Extensive use of Perl, TCL, python or other scripting languages.
Experience developing specifications in the early design phase and customer ready IP datasheets and user guides for use in design deployment.
Familiarity with overall chip design methodologies and tools
Additional Job Description:
Compensation and Benefits
The annual base salary range for this position is $101,000 - $162,000
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.