Datacenter Power and Performance Modeling Engineer 

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE: 

AMD’s Datacenter Performance Group is seeking talented, motivated engineers to drive the Power Constrained Performance of our industry-leading AI/ML/HPC GPUs. The role will involve many aspects of Perf@Power attainment, including pre-Si power modeling, post-Si correlation, workload analysis, setting PPA targets and driving attainment, power/perf roll-ups and reporting, methodology innovations and development. Being passionate about performance and power efficiency is a key ingredient for success in this role.

THE PERSON: 

You have a passion for performance and power efficiency. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

KEY RESPONSIBILITIES:

• Pre-silicon power modeling (HW-IP, SoC, Multi-GPU nodes/clusters), Power-constrained Performance projections and Reporting
• Support Pre-silicon PPA target setting (for HW IPs, FW and SW)
• Support PPA attainment by working with various engineering functions including SOC architecture, System Design, IP Design, Foundry team, Physical Design, Software, Power Management, Post-si validation
• Post Si calibration of models and Power/Performance debug
• Analyzing key workloads for power behaviors and optimization opportunities
• Scripting and coding to automate routine tasks, building new tools for wider usage

KEY QUALIFICATIONS:

• Background in Computer Architecture, Power and Performance
• Experience in Soc Level Power/Performance projections, modeling and optimization
• Experience in power modeling for digital and analog IPs
• Familiarity with digital logic physical design and power management techniques (clock gating, power gating, V-F curves, p-states, on-die voltage regulation, clock integrity, etc..)
• Verilog RTL coding experience/understanding is desirable, especially low power design techniques
• Experience in post-silicon power/performance debug, model correlation 
• Knowledge of DL/ML/LLM workloads will be a bonus
• Fluency in Excel based data analysis & charting, scripting experience in Ruby, Python

ACADEMIC CREDENTIALS: 

• Bachelors or Masters degree in Computer Engineering/Electrical Engineering 

#LI-RL1

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.