FPGA Design Engineer (Timing)
AMD · San Jose, CA · Engineering
About this role
AMD is hiring a mid-level Systems Engineer in the operations function based in San Jose, CA. The posting calls out experience with Python, Embedded Systems.
- Role
- Systems Engineer
- Function
- operations
- Level
- mid
- Track
- Individual contributor
- Location
- San Jose, CA
- Department
- Engineering
- Posted
- Apr 29, 2026
More roles at AMD
Job description
from AMD careersWHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
As a FPGA Design Engineer, you will work with digital timing experts, FPGA circuit designers and FPGA software modeling experts to create timing model for the entire FPGA, that will be used by the FPGA toolset to ensure proper timing for the user created designs.
THE PERSON:
You have a passion for digital design, and associated timings based on various operating conditions (PVT) to ensure correct functionality of a complex design. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.