Senior Analog Layout Design Engineer
AMD · Penang, Malaysia · Engineering
About this role
AMD is hiring a senior-level Hardware Engineer in the software engineering function based in Penang, Malaysia (hybrid). The posting calls out experience with Embedded Systems and roughly 5+ years of relevant work. Listed education preference: a associate's degree or equivalent.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- senior
- Track
- Individual contributor
- Location
- Penang, Malaysia
- Work mode
- Hybrid
- Experience
- 5+ years
- Education
- Associate's degree
- Department
- Engineering
- Posted
- Apr 27, 2026
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Job description
from AMD careersWHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
AMD is looking for a candidate to design the layout for digital and analog circuits based on schematics using industry leading CAD tools and cutting-edge foundry technology. Examples of layout designed by our team include Phase Locked Loop (PLL), Delay Locked Loop (DLL), Voltage Controlled Oscillator (VCO), Digital to Analog Converter (DAC), Current Regulator, High Speed Differential Signalling circuitry, Droop Detect, and Die Crack Monitor. Proficiency in 2D layout design while being able to visualize in 3D space are traits ideal for this position. It is useful to have knowledge of digital and analog circuitry at the CMOS transistor level.