FPGA Power Management Engineer
AMD · San Jose, CA · Engineering
About this role
AMD is hiring a mid-level Hardware Engineer in the software engineering function based in San Jose, CA. The posting calls out experience with Performance Optimization, Embedded Systems.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- mid
- Track
- Individual contributor
- Location
- San Jose, CA
- Department
- Engineering
- Posted
- Apr 30, 2026
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Job description
from AMD careersWHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
We are seeking an experienced FPGA Power Management Engineer to join AMD’s FPGA Power Architecture team, helping bring adaptive, workload‑aware power management capabilities into next‑generation FPGA platforms.
In this role, you will architect, implement, and validate closed‑loop DVFS (Dynamic Voltage and Frequency Scaling) and adaptive voltage scaling systems, bridging architecture, RTL, firmware, and lab validation. This is a hands‑on position with real impact on production silicon, focused on improving performance‑per‑watt across demanding data center and defense use cases.
As an early hire in this effort, you will play a key role in shaping how power intelligence is designed, validated, and deployed across AMD FPGA platforms.