ASIC/SoC Design Engineer, RTL design for SoC IPs
AMD · San Jose, CA · Engineering
About this role
AMD is hiring a mid-level Systems Engineer in the operations function based in San Jose, CA. The posting calls out experience with Python, Embedded Systems.
- Role
- Systems Engineer
- Function
- operations
- Level
- mid
- Track
- Individual contributor
- Location
- San Jose, CA
- Department
- Engineering
- Posted
- Feb 19, 2026
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Job description
from AMD careersWHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
Join AMD's Silicon Design team to design and develop cutting-edge IPs for next-generation embedded products. As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design.
THE PERSON:
The ideal candidate is a seasoned ASIC/SOC designer with proven expertise across the entire chip development lifecycle—from RTL design through silicon bring-up. You excel in Verilog RTL coding, timing closure, and physical design awareness. With multiple production tape-outs under your belt, you bring deep technical expertise, strong ownership, and the ability to mentor junior engineers while driving projects to successful completion.