Senior SoC Design Engineer
AMD · San Jose, CA · Engineering
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
Lead the design and delivery of next-generation features for advanced AMD SoCs, driving innovation from concept through silicon bring-up. You will play a key role in enabling high-performance, scalable, and power-efficient solutions for cutting-edge AMD platforms.
THE PERSON:
You are a highly skilled digital design engineer with deep expertise in modern processor architectures and SoC development. You thrive in collaborative, fast-paced environments and bring hands-on experience with high-speed interfaces such as PCIe, USB, Ethernet, and/or CXL.
You combine strong analytical problem-solving skills with technical ownership, attention to quality, and a continuous learning mindset. You communicate effectively across global, cross-functional teams and are comfortable driving complex technical initiatives to completion.
KEY RESPONSIBILITIES:
- Design and integrate hard macros, functional units, subsystems, and third‑party IP into SoC designs.
- Execute all phases of the SoC design flow, including high‑level design and methodology development.
- Collaborate closely with architecture, verification, system validation, physical design, and DFT teams to ensure successful tape‑out.
- Deliver designs on schedule with a strong focus on quality.
- Support silicon bring‑up for owned features.
PREFERRED EXPERIENCE:
Professional experience focused on ASIC IP integration and block‑level RTL design
- Quality checks such as Lint and CDC.
- Experienced in AXI protocol and high‑speed interfaces (PCIe, CXL, Ethernet, USB).
- Simulation, debug, and block‑level verification development.
- Synthesis, constraint development, STA, and ECO.
- Scripting and automation using Perl, Python, or Tcl.
- PPA trade‑off analysis and decision‑making.
- Working knowledge of AI‑assisted productivity tools (e.g., Copilot).
- Clear and effective written and verbal communication.
ACADEMIC CREDENTIALS:
Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering.
LOCATION: San Jose, CA
This position is not eligible for Visa sponsorship
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Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.