Design Verification Engineer - ASIC/UVM/SystemVerilog
AMD · Santa Clara, CA · Engineering
About this role
AMD is hiring a mid-level Hardware Engineer in the software engineering function based in Santa Clara, CA. The posting calls out experience with Python, C, Testing, Embedded Systems. Listed education preference: a bachelor's degree or equivalent.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- mid
- Track
- Individual contributor
- Location
- Santa Clara, CA
- Education
- Bachelor's degree
- Department
- Engineering
- Posted
- Feb 10, 2026
More roles at AMD
Job description
from AMD careersWHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
AMD’s Network Technologies Solutions Group (NTSG) is a leading provider of advanced data center networking technology. Our distributed services platform expands AMD’s data center product portfolio with a high‑performance DPU and software stack deployed at scale across major cloud and enterprise environments, including Goldman Sachs, IBM Cloud, Microsoft Azure, and Oracle.
THE PERSON:
We are seeking a high‑impact MTS Design Verification Engineer with strong technical depth, ownership, and the ability to drive verification closure on complex, high‑performance ASIC designs.
The ideal candidate brings hands‑on verification expertise, excels in debugging intricate architecture/RTL issues, and is comfortable leading verification efforts across IP, subsystem, and SoC levels.