Senior FPGA Engineer, LEO Payload FPGA
Amazon · Sunnyvale, CA · Software Development
About this role
Amazon is hiring a senior-level Embedded Software Engineer in the software engineering function based in Sunnyvale, CA. The posting calls out experience with Python, Embedded Systems and roughly 7+ years of relevant work. Listed education preference: a bachelor's degree or equivalent. Compensation is listed at $183,000–$247,600 per year.
- Role
- Embedded Software Engineer
- Function
- software engineering
- Level
- senior
- Track
- Individual contributor
- Employment
- Full-time
- Location
- Sunnyvale, CA
- Experience
- 7+ years
- Education
- Bachelor's degree
- Visa
- Not sponsored
- Department
- Software Development
- Posted
- Feb 27, 2026
More roles at Amazon
Job description
from Amazon careersLEO is Amazon’s low Earth orbit satellite broadband network. Its mission is to deliver fast, reliable internet to customers and communities around the world, and we’ve designed the system with the capacity, flexibility, and performance to serve a wide range of customers, from individual households to schools, hospitals, businesses, government agencies, and other organizations operating in locations without reliable connectivity. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Key job responsibilities Create FPGA solutions to support LEO's satellite communication system. This is a unique opportunity to define a new system with few legacy constraints. The FPGA design engineer will work with systems teams to define/develop/implement/test/release FPGA based solutions to enable LEO. This will focus on creating digital designs for networking functions using the latest generations of FPGA technologies and modern FPGA design processes and tools. In this role you will: Have ownership of one or more FPGA bitstreams. - Create and release FPGAs through the development phases of uArchitecture-RTL Design-Physical Implementation-Timing Closure–Simulation Validation– Lab Based Silicon Validation Collaborate with…