Sr. Package Layout Engineer, Annapurna Labs - AI Silicon Packaging
Amazon · IL · Hardware Development
senior
software engineering
Hardware Engineer
ic
· Posted May 13, 2026
Skills
About this role
Amazon is hiring a senior-level Hardware Engineer in the software engineering function based in IL. The posting calls out experience with Python, C, AWS, Git.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- senior
- Track
- Individual contributor
- Employment
- Full-time
- Location
- IL
- Department
- Hardware Development
- Posted
- May 13, 2026
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Job description
from Amazon careersAnnapurna Labs (our organization within AWS) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.
We are seeking a Sr. Package Layout Engineer to lead the end-to-end physical design of advanced IC packages for next-generation machine learning and data center ASICs.
In this role, you will own the package layout from initial floor planning through tape out and manufacturing release. You'll drive the physical implementation of complex multi-die and advanced packaging architectures, working closely with silicon, SI/PI, thermal, and manufacturing teams to deliver production-ready designs that meet dynamic performance, density, and reliability targets.
Key job responsibilities
Lead the full package layout cycle from die floor planning, bump/pad assignment, and RDL routing through substrate design, verification, and tape out release.
Drive physical design of advanced packaging architectures including 2.5D interposer, 3D-IC, fan-out wafer-level packaging, and silicon bridge technologies (e.g., CoWoS, EMIB, or similar).
Define and optimize package floorplans considering die placement, bump maps, power/ground distribution, high-speed signal escape routing, and decoupling capacitor placement.
Perform detailed RDL and substrate routing for high-density interconnects including microbumps, C4 bumps, TSVs, microvias, and PTH vias across multi-layer organic substrates and silicon interposers.
Participate in die-level RDL routing and bump planning in coordination with ASIC physical design teams, ensuring the die-package interface is co-optimized for power delivery and signal routing from the earliest design stages.
Drive cross-level layout co-optimization across die RDL, interposer/substrate, and PCB levels to achieve the best overall power delivery network and high-speed signaling performance, minimizing impedance discontinuities and routing bottlenecks at each interface boundary.
Develop and maintain package stack-up definitions in collaboration with SI/PI and materials engineering teams, ensuring impedance targets, layer utilization, and manufacturing constraints are met.
Create and enforce package design rules and guidelines, working with OSAT partners and foundries to ensure DFM compliance and high yield.
Run and review physical verification checks (DRC, connectivity, shorts/opens) and drive design closure with zero escapes.
Manage package design schedules, milestones, and deliverables, coordinating across multiple concurrent projects and tape out cycles.
Collaborate with SI/PI engineers to incorporate electrical constraints into the physical layout — impedance-controlled routing, power plane optimization, and critical net shielding.
Interface with OSAT vendors and foundry partners on substrate and interposer manufacturing feasibility, design rule negotiations, and process capability alignment.
Identify packaging technology risks early and propose design or process mitigations to ensure reliability and manufacturability.
Mentor junior layout engineers and contribute to the development of team best practices, automation flows, and design reuse strategies.
About the team
Our team is dedicated to supporting new members. We have a broad mix of experience levels and tenures, and we’re building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind, code reviews. We care about your career growth and strive to assign projects that help our team members develop your engineering expertise so you feel empowered to take on more complex tasks in the future.
Diverse Experiences
AWS values diverse experiences. Even if you do not meet all of the qualifications and skills listed in the job description, we encourage candidates to apply. If your career is just starting, hasn’t followed a traditional path, or includes alternative experiences, don’t let it stop you from applying.
About AWS
Amazon Web Services (AWS) is the world’s most comprehensive and broadly adopted cloud platform. We pioneered cloud computing and never stopped innovating — that’s why customers from the most successful startups to Global 500 companies trust our robust suite of products and services to power their businesses.
Inclusive Team Culture
Here at AWS, it’s in our nature to learn and be curious. Our employee-led affinity groups foster a culture of inclusion that empower us to be proud of our differences. Ongoing events and learning experiences, including our Conversations on Race and Ethnicity (CORE) and AmazeCon (gender diversity) conferences, inspire us to never stop embracing our uniqueness.
Work/Life Balance
We value work-life harmony. Achieving success at work should never come at the expense of sacrifices at home, which is why we strive for flexibility as part of our working culture. When we feel supported in the workplace and at home, there’s nothing we can’t achieve in the cloud.
Mentorship & Career Growth
We’re continuously raising our performance bar as we strive to become Earth’s Best Employer. That’s why you’ll find endless knowledge-sharing, mentorship and other career-advancing resources here to help you develop into a better-rounded professional.
- 7+ years of digital design in communication systems experience
- 7+ years of full-custom analog or RF layout experience
- 7+ years of wireless communications systems and implementation experience
- 8+ years of creating and maintaining automation frameworks for Post-Silicon Flow experience
- 7+ years of verification in communication systems experience
- 5+ years of UVM, C, System C, and scripting experience
- 3+ years of emulation experience
- Bachelor's degree in Electrical Engineering or a related field
- Knowledge of UVM and Matlab
- Knowledge of implementing chips with multiple power islands and power gating
- Knowledge of multiple access systems including OFDMA, TDMA, and CDMA
- Knowledge of end-to-end network system architecture from wireless physical layer to application endpoints
- Knowledge of serial protocols including SPI, I2C, I3C, and UART
- Knowledge of Python and Embedded C programming
- Experience in communication theory, OFDM, MIMO, Digital/Wireless Communication Systems or RF engineering
- Experience with current and upcoming RF standards in cellular (4G/5G), WiMAX, 802.11ad, microwave backhaul, DVB-S2 / DVB-C, or related broadband wireless standards
- Experience leading or solely developing methodology and scripts for physical synthesis
- Experience taping out chips that have gone into high volume production
- Experience developing products for volume production
- Experience low power design techniques
- Experience delivering products to volume production
- Experience in modem L1/L2 algorithms development and architectures
- Experience in developing link and system level simulators using MATLAB, Python, or C++
- Experience in test setup automation using MATLAB, Python, or Pearl
- Experience with Agile, TDD, BDD, CI, and Git
- Experience developing PHY/MAC layer HW/SW targeting SoCs, FPGAs, and general-purpose processors
- Experience leading technical initiatives and key deliverables
- Experience with version control systems and CI/CD pipeline implementation
- Experience in Bare Metal Environment development, including linker scripts, page tables and NVIC
- Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs
- Experience with modern ASIC/FPGA design and verification tools
- Experience with SOC bring-up and post-silicon validation
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.
We are seeking a Sr. Package Layout Engineer to lead the end-to-end physical design of advanced IC packages for next-generation machine learning and data center ASICs.
In this role, you will own the package layout from initial floor planning through tape out and manufacturing release. You'll drive the physical implementation of complex multi-die and advanced packaging architectures, working closely with silicon, SI/PI, thermal, and manufacturing teams to deliver production-ready designs that meet dynamic performance, density, and reliability targets.
Key job responsibilities
Lead the full package layout cycle from die floor planning, bump/pad assignment, and RDL routing through substrate design, verification, and tape out release.
Drive physical design of advanced packaging architectures including 2.5D interposer, 3D-IC, fan-out wafer-level packaging, and silicon bridge technologies (e.g., CoWoS, EMIB, or similar).
Define and optimize package floorplans considering die placement, bump maps, power/ground distribution, high-speed signal escape routing, and decoupling capacitor placement.
Perform detailed RDL and substrate routing for high-density interconnects including microbumps, C4 bumps, TSVs, microvias, and PTH vias across multi-layer organic substrates and silicon interposers.
Participate in die-level RDL routing and bump planning in coordination with ASIC physical design teams, ensuring the die-package interface is co-optimized for power delivery and signal routing from the earliest design stages.
Drive cross-level layout co-optimization across die RDL, interposer/substrate, and PCB levels to achieve the best overall power delivery network and high-speed signaling performance, minimizing impedance discontinuities and routing bottlenecks at each interface boundary.
Develop and maintain package stack-up definitions in collaboration with SI/PI and materials engineering teams, ensuring impedance targets, layer utilization, and manufacturing constraints are met.
Create and enforce package design rules and guidelines, working with OSAT partners and foundries to ensure DFM compliance and high yield.
Run and review physical verification checks (DRC, connectivity, shorts/opens) and drive design closure with zero escapes.
Manage package design schedules, milestones, and deliverables, coordinating across multiple concurrent projects and tape out cycles.
Collaborate with SI/PI engineers to incorporate electrical constraints into the physical layout — impedance-controlled routing, power plane optimization, and critical net shielding.
Interface with OSAT vendors and foundry partners on substrate and interposer manufacturing feasibility, design rule negotiations, and process capability alignment.
Identify packaging technology risks early and propose design or process mitigations to ensure reliability and manufacturability.
Mentor junior layout engineers and contribute to the development of team best practices, automation flows, and design reuse strategies.
About the team
Our team is dedicated to supporting new members. We have a broad mix of experience levels and tenures, and we’re building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind, code reviews. We care about your career growth and strive to assign projects that help our team members develop your engineering expertise so you feel empowered to take on more complex tasks in the future.
Diverse Experiences
AWS values diverse experiences. Even if you do not meet all of the qualifications and skills listed in the job description, we encourage candidates to apply. If your career is just starting, hasn’t followed a traditional path, or includes alternative experiences, don’t let it stop you from applying.
About AWS
Amazon Web Services (AWS) is the world’s most comprehensive and broadly adopted cloud platform. We pioneered cloud computing and never stopped innovating — that’s why customers from the most successful startups to Global 500 companies trust our robust suite of products and services to power their businesses.
Inclusive Team Culture
Here at AWS, it’s in our nature to learn and be curious. Our employee-led affinity groups foster a culture of inclusion that empower us to be proud of our differences. Ongoing events and learning experiences, including our Conversations on Race and Ethnicity (CORE) and AmazeCon (gender diversity) conferences, inspire us to never stop embracing our uniqueness.
Work/Life Balance
We value work-life harmony. Achieving success at work should never come at the expense of sacrifices at home, which is why we strive for flexibility as part of our working culture. When we feel supported in the workplace and at home, there’s nothing we can’t achieve in the cloud.
Mentorship & Career Growth
We’re continuously raising our performance bar as we strive to become Earth’s Best Employer. That’s why you’ll find endless knowledge-sharing, mentorship and other career-advancing resources here to help you develop into a better-rounded professional.
Basic Qualifications
- 7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience- 7+ years of digital design in communication systems experience
- 7+ years of full-custom analog or RF layout experience
- 7+ years of wireless communications systems and implementation experience
- 8+ years of creating and maintaining automation frameworks for Post-Silicon Flow experience
- 7+ years of verification in communication systems experience
- 5+ years of UVM, C, System C, and scripting experience
- 3+ years of emulation experience
- Bachelor's degree in Electrical Engineering or a related field
- Knowledge of UVM and Matlab
- Knowledge of implementing chips with multiple power islands and power gating
- Knowledge of multiple access systems including OFDMA, TDMA, and CDMA
- Knowledge of end-to-end network system architecture from wireless physical layer to application endpoints
- Knowledge of serial protocols including SPI, I2C, I3C, and UART
- Knowledge of Python and Embedded C programming
- Experience in communication theory, OFDM, MIMO, Digital/Wireless Communication Systems or RF engineering
- Experience with current and upcoming RF standards in cellular (4G/5G), WiMAX, 802.11ad, microwave backhaul, DVB-S2 / DVB-C, or related broadband wireless standards
- Experience leading or solely developing methodology and scripts for physical synthesis
- Experience taping out chips that have gone into high volume production
- Experience developing products for volume production
- Experience low power design techniques
- Experience delivering products to volume production
- Experience in modem L1/L2 algorithms development and architectures
- Experience in developing link and system level simulators using MATLAB, Python, or C++
- Experience in test setup automation using MATLAB, Python, or Pearl
- Experience with Agile, TDD, BDD, CI, and Git
- Experience developing PHY/MAC layer HW/SW targeting SoCs, FPGAs, and general-purpose processors
- Experience leading technical initiatives and key deliverables
- Experience with version control systems and CI/CD pipeline implementation
- Experience in Bare Metal Environment development, including linker scripts, page tables and NVIC
Preferred Qualifications
- Master's degree or Ph.D. degree in Electrical Engineering or related field- Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs
- Experience with modern ASIC/FPGA design and verification tools
- Experience with SOC bring-up and post-silicon validation
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.