Design Verification Engineer, Silicon and Systems Group

Job description

As a Design Verification (DV) Engineer, you will be part of an advanced architecture team that is exploring new hardware designs to improve our devices. In this role, you will be responsible for defining the verification methodology and implementing the corresponding test plan for advanced functional blocks. You will participate in the design verification and bring-up of such blocks by writing relevant assertions, debugging code, test benches, test harnesses, and otherwise interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware Engineering, and Software Engineering, to architect and implement complex functional block that enable development of world-class hardware devices. In this role, you will: · Design world class hardware and software · Communicate and work with team members across multiple disciplines · Deliver detailed test plans for verification of complex digital design blocks by working with design engineers and architects · Create and enhance constrained-random verification environments using SystemVerilog and UVM · Identify and write all types of coverage measures for stimulus and corner-cases. · Debug tests with design engineers to deliver functionally correct design blocks. · Close coverage measures to identify verification holes and to show progress towards tape-out.…