Physical Design Timing Engineer (STA)

Job description

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Job Description:

The Full Chip Static Timing Analysis (STA) Engineer is responsible for ensuring that ASIC meets its performance targets and timing requirements across all operating conditions.

Key Responsibilities:

• Full-Chip Timing Sign-off: Own the final timing closure for ASIC, performing quality checks across all process, voltage, and temperature (PVT) corners

• Constraint Development: Author, validate, and maintain SDC for various modes, including functional and test modes (Scan, MBIST,ATPG)

• Analyze foundry guidelines and work with the team to incorporate sign off corners, margins, and derates into timing analysis flows and methodologies

• Advanced Timing Concepts: Deep knowledge of On-Chip Variation (AOCV/POCV), Signal Integrity (crosstalk), and IR-drop aware STA

• Multi-Mode Multi-Corner (MMMC) Analysis: Manage and analyze hundreds of timing scenarios to ensure reliability across diverse operating environments

• Timing ECOs: Automate, generate and implement ECOs to fix setup, hold, and transition violations  in the design cycle

• Scripting: High proficiency in Tcl (primary for EDA tools), Python, and Perl for automating analysis flows and data mining.

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