mid software engineering Hardware Engineer ic 10+ yrs Bachelor's · Posted May 22, 2026
$127,100 – $203,400
USD per year

About this role

Broadcom is hiring a mid-level Hardware Engineer in the software engineering function based in USA-Colorado-Fort Collins-4380 Ziegler Road. The posting calls out experience with Linux, System Design and roughly 10+ years of relevant work. Listed education preference: a bachelor's degree or equivalent. Compensation is listed at $127,100–$203,400 per year.

Role
Hardware Engineer
Function
software engineering
Level
mid
Track
Individual contributor
Employment
Full-time
Location
USA-Colorado-Fort Collins-4380 Ziegler Road
Experience
10+ years
Education
Bachelor's degree
Posted
May 22, 2026
AI Summary
SerDes Digital IP Design Engineer responsible for architecture design, RTL development, synthesis, timing analysis, and verification. Requires expertise in Spyglass, Design Compiler, and PrimeTime tools with deep knowledge of VLSI design flows, CDC analysis, and constraints development.

More roles at Broadcom

R&D IC Design Engineer
USA-CA Irvine Alton Parkway Bldg 2 · mid
Testing Python Linux
Infrastructure Design Automation Engineer
USA-Colorado-Fort Collins-4380 Ziegler Road · mid
Ruby Bash Git
IP Integration Engineer
USA-Colorado-Fort Collins-4380 Ziegler Road · mid
Python Ruby Bash
Quality Ops Engineer 4
USA-California-San Jose-1320 Ridder Park Drive · mid
Wafer Fabrication Operator 2
USA-Colorado-Fort Collins-4380 Ziegler Road · mid
All Broadcom jobs →

Job description

from Broadcom careers

Please Note:

1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)

2. If you already have a Candidate Account, please Sign-In before you apply.

Job Description:

Digital Design: SerDes Digital IP Design Engineer:

Oversees definition, design, verification co-definition, and documentation for SerDes development. Performs architecture design, rtl development, constraints, synthesis, timing analysis, verification, documentation, and support for SerDes designs.  Knowledge of all aspects of the process flow from high-level RTL design to synthesis, RTL/ netlist audits (using tools such as Spyglass), Formal verification, constraints development and analysis w/ emphasis on CDCs in the context of synthesis and over all use in PrimeTime, Timing model generation (ETM/ .db).   Emphasis on Spyglass lint, CDC and abstract model generation along with design constraint and timing analysis.

Knowledge:  

Synthesis flows (design compiler or newer tools), lint and CDC analysis (spyglass), constraints development and timing model creation (primetime) along with formality is desired.  Knowledge of SerDes architecture and protocols are a plus.  Knowledge of spyglass, VC spyglass, design compiler and primetime is a must.

Job Complexity:

This is an excerpt. Read the full job description on Broadcom careers →
All software engineering jobs software engineering salaries software engineering career path
All Broadcom Jobs Browse software engineering roles mid positions